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Part: AT45DB161B-RI

Category: category

Description: -

Company: company

Datasheet : download   File size : 250 kB

Datasheet text preview:
Features
· · · · · · · · · · · · · · ·
100% Compatible to AT45DB161 Single 2.7V - 3.6V Supply Serial Interface Architecture Page Program Operation ­ Single Cycle Reprogram (Erase and Program) ­ 4096 Pages (528 Bytes/Page) Main Memory Optional Page and Block Erase Operations Two 528-byte SRAM Data Buffers ­ Allows Receiving of Data while Reprogramming of Nonvolatile Memory Continuous Read Capability through Entire Array Internal Program and Control Timer Low Power Dissipation ­ 4 mA Active Read Current Typical ­ 2 µA CMOS Standby Current Typical 20 MHz Max Clock Frequency Hardware Data Protection Feature Serial Peripheral Interface (SPI) Compatible ­ Modes 0 and 3 CMOS and TTL Compatible Inputs and Outputs 5.0V-tolerant Inputs: SI, SCK, CS, RESET and WP Pins Commercial and Industrial Temperature Ranges

16-megabit 2.7-volt Only Serial DataFlash® AT45DB161B

Description
T h e AT45DB161B is a 2.7-volt only, serial interface Flash memory suitable for i n -s y s t em reprogramming. Its 17,301,504 bits of memory are organized as 4096 pa ge s of 528 bytes each. In addition to the main memory, the AT45DB161B also contains two SRAM data buffers of 528 bytes each. The buffers allow receiving of data (continued)

Pin Configurations
Pin Name CS SCK SI SO WP RESET RDY/BUSY Function Chip Select Serial Clock Serial Input Serial Output Hardware Page Write Protect Pin Chip Reset Ready/Busy
GND NC NC CS SCK SI SO NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RDY/BUSY RESET WP NC NC VCC GND NC NC NC CS SCK SI SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14

TSOP Top View Type 1
28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC

SOIC
28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC NC NC WP RESET RDY/BUSY NC NC NC NC NC NC NC NC

CBGA Top View through Package
1 2 3 4 5

A
NC NC NC NC NC NC

B
NC SCK GND VCC CS RDY/BSY WP SO NC

C
NC

D
NC SI RESET NC NC NC NC

E
NC

Rev. 2224B­03/01

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while a page in the main memory is being reprogrammed. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a serial interface to sequentially access its data. The simple s e r i a l interface facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. The device is optimized for use in many commercial and industrial applications where high density, low p i n count, low voltage, and low power are essential. Typical applications for the DataFlash are digital voice storage, image storage, and data storage. The device operates at clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA. To allow for simple in-system reprogrammability, the AT45DB161B does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB161B is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming cycles are self-timed, and no separate erase cycle is required before programming.

Block Diagram
WP FLASH MEMORY ARRAY

PAGE (528 BYTES)

BUFFER 1 (528 BYTES)

BUFFER 2 (528 BYTES)

SCK CS RESET VCC GND RDY/BUSY

I/O INTERFACE

SI

SO

Memory Array

To provide optimal flexibility, the memory array of the AT45DB161B is divided into three levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis; however, the optional erase operations can be performed at the block or page level.

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AT45DB161B
Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0 = 8 Pages 4,224 bytes (4K + 128) SECTOR 1 = 248 Pages 130,944 bytes (124K + 3,968)

BLOCK ARCHITECTURE
SECTOR 0
BLOCK 0 BLOCK 1

PAGE ARCHITECTURE
8 Pages
PAGE 0 PAGE 1

SECTOR 1

SECTOR 2 = 256 Pages 135,168 bytes (128K + 4K)

BLOCK 30 BLOCK 31 BLOCK 32

BLOCK 0

PAGE 6 PAGE 7 PAGE 8

SECTOR 2

SECTOR 3 = 256 Pages 135,168 bytes (128K + 4K)

BLOCK 62 BLOCK 63 BLOCK 64 BLOCK 65 BLOCK 66

BLOCK 1

BLOCK 33

PAGE 9

PAGE 14 PAGE 15 PAGE 16 PAGE 17 PAGE 18

SECTOR 16 = 256 Pages 135,168 bytes (128K + 4K)

BLOCK 509 BLOCK 510 BLOCK 511

PAGE 4093 PAGE 4094 PAGE 4095

Block = 4224 bytes (4K + 128)

Page = 528 bytes (512 + 16)

Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses and data are transferred with the most significant bit (MSB) first. Buffer addressing is referenced in the datasheet using the terminology BFA9 - BFA0 to denote the ten address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA11 - PA0 and BA9 - BA 0 where PA11 - PA0 denotes the 12 address bits required to designate a page address and BA9 - BA0 denotes the ten address bits required to designate a byte address within the page.

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from e i th e r one of the two data buffers. The DataFlash supports two categories of read modes in relation to the SCK signal. The differences between the modes are in respect to the inactive state of the SCK signal as well as which clock cycle data will begin to be output. The two categories, which are comprised of four modes total, are defined as In a c ti v e Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to Table 1 on page 11 for a complete list) is used to select which category will be used for reading. Please refer to the "Detailed Bit-level Read Timing" diagrams in this datasheet for details on the clock cycle sequences for each mode. CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock 3

2224B­03/01

cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked into the device followed by 24 address bits and 32 don't care bits. The first two bits of the 24-bit address sequence are reserved for upward and downward compatibility to l a r g e r and smaller density devices (see Notes under "Command Sequence for Read/Write Operations" diagram). The next 12 address bits (PA11 - PA0) specify which page of the main memory array to read, and the last ten bits (BA9 - BA0) of the 24-bit address sequence specify the starting byte address within the page. The 32 don't care bits that follow the 24 address bits are needed to initialize the read operation. Following the 32 don't care bits, additional clock pulses on the SCK pin will result in serial data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bits, the don't care bits, and the reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the S O pin. The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. BURST ARRAY READ: The Burst Array Read operation functions almost identically to the Continuous Array Read operation but allows much higher read throughputs by utilizing faster clock frequencies. The Burst Array Read command allows the device to burst an entire page of data out at the maximum SCK frequency defined by the fBAR parameter. Differences between the Burst Array Read and Continuous Array Read operations a r e limited to timing only. The opcodes utilized and the opcode and addressing sequence for the Burst Array Read are identical to the Continuous Array Read. The opcode of 68H or E8H must be clocked into the device followed by the 24 address bits and 32 don't care bits. Following the 32 don't care bits, additional clock pulses on the SCK pin will result in serial data being output on the SO (serial output) pin. As with the Continuous Array Read, the CS pin must remain low during the loading of the opcode, the address bits, the don't care bits, and the reading of data. During a Burst Array Read, when the end of a page in main memory is reached (the last bit of the page has been clocked out), the system must delay the next SCK pulse by a minimum time of tBRBD. This delay is necessary to allow the device enough time to cross over the burst read boundary, which is defined as the end of one page in memory to the beginning of the next page. When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. The transition from the last bit of the array back to the beginning of the array is also considered a burst read boundary. Therefore, the system must delay the SCK pulse that will be used to read the first bit of the memory array by a minimum time of tBRBD. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. The maximum SCK frequency allowable for the Burst Array Read is defined by the fBAR specification. The Burst Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

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AT45DB161B
MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data directly from any one of the 4096 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read, an opcode of 52H or D2H must be clocked into the device followed by 24 address bits and 32 don't care bits. The first two bits of the 24-bit address sequence are reserved bits, the next 12 address bits (PA11 - PA0) specify the page address, and the next ten address bits (BA9 - BA0) specify the starting byte address within the page. The 32 don't care bits which follow the 24 address bits are sent to initialize the read operation. Following the 32 don't care bits, additional pulses on SCK result in serial data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bits, the don't care bits, and the reading of data. When the end of a page in main memory is reached during a Main Memory Page Read, the device will continue reading at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the eight bits of the opcode must be followed by 14 don't care bits, ten address bits, and eight don't care bits. Since the buffer size is 528 bytes, ten address bits (BFA9 - BFA0) are required to specify the first byte of data to be read from the buffer. The CS pin must remain low during the loading of the opcode, the address bits, the don't care bits, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. STATUS REGISTER READ: The status register can be used to determine the device's Ready/Busy status, the result of a Main Memory Page to Buffer Compare operation, or t he device density. To read the status register, an opcode of 57H or D7H must be loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The five most significant bits of the status register will contain device information, while the remaining three least-significant bits are reserved for future use and will have undefined values. After bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting again with bit 7. The data in the status register is constantly updated, so each repeating sequence will output new data.

Status Register Format
Bit 7 RDY/BUSY Bit 6 COMP Bit 5 1 Bit 4 0 Bit 3 1 Bit 2 X Bit 1 X Bit 0 X

Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state. The user can continuously poll bit 7 of the status register by stopping SCK once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and once the device is no longer busy, the state of SO will change from 0 to 1. There are eight operations which can cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program with Built-in Erase, Buffer to Main Memory Page Program without Built-in Erase, Page Erase, Block Erase, Main Memory Page Program, and Auto Page Rewrite.

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